Products
ARISTO Processor
The Parsé ARISTO processor is a synthesizable VHDL model of a 32-bit processor similar to the SPARC V8 architecture.
Features
The ARISTO is a 32-bit processor conforming to the IEEE 1754 (SPARC V8) architecture. It is designed for embedded applications with the following features on-chip:
- IEEE 1754 compliant integer unit with 5-stage pipeline
- Hardware multiply, divide and MAC units
- Arbitrary Size Register File Interface
- Floating Point Unit Interface
- Coprocessor Interface
- Cache Interface
- Interrupt In
- Debug Support + Debug Interface
- Cache controller:
- 2 way set-associative caches
- Replacement Method: LRR ( Least Recently Replaced )
- Interface to arbitrary size memories for Data Cache & Instruction Cache (Data and Tag)
- Interface to arbitrary size local RAM
- AHB Master
- Separate instruction and data caches (Harvard architecture)
- Cache+MMU Controller:
- Interface to arbitrary size memories for Data Cache & Instruction Cache (Data and Tag)
- Interface to arbitrary size local RAM
- AHB Master
- Six basic categories of instructions: (Load/Store, Arithmetic/Logical/Shift, Control Transfer, Read/Write Control Register, Floating-Point Operate, Coprocessor Operate)
- Condition codes
- Few and simple instruction formats
- Few addressing modes
- Triadic register addresses
For performance evaluation, Dhrystone benchmark was ran on TACHRA. Execution result shows 1400 iteration/s/MHz using our compiler.
New modules can easily be added using the on-chip AMBA AHB/APB buses.
