Products
TINY Processor
The Parsé TINY processor is a synthesizable VHDL model of a 32-bit processor similar to the IEEE 1754 (SPARC V8) architecture. TINY is a tiny model of ARISTO processor for FPGA/ASIC fast applications that may not need cache and other peripheries.
Features
- IEEE 1754 compliant integer unit with 4-stage pipeline
- Hardware multiplier
- Debug Support Unit (DSU)
- Floating Point Unit Interface
- Coprocessor Interface
- Interrupt In
- Local instruction and Data Memory
- Six basic categories of instructions: (Load/Store, Arithmetic/Logical/Shift, Control Transfer, Read/Write Control Register, Floating-Point Operate, Coprocessor Operate)
- Condition codes
- Few and simple instruction formats
- Few addressing modes
- Triadic register addresses
- Low Power Enhancements
For performance evaluation, Dhrystone benchmark was ran for TINY processor. Execution result shows 1320 iteration/s/MHz using our compiler.
New modules can easily be added using the on-chip AMBA AHB/APB buses.
| Device | Process | Area | Frequency (MHz) |
| VIRTEX-4 | -10 | 3200 LUTs | 140 |
| VIRTEX-II | -6 | 2000 LUTs | 91 |
| Cyclone | -6 | 2300 LCs | 82 |